(NanoRealm) - Researchers at Tyndall National Institute in Cork, Ireland led by professor Jean-Pierre Colinge have reported in Nature Nanotechnology how they have designed and fabricated what is claimed to be the first junctionless transistor, which could significantly reduce power consumption and simplify the fabrication process for silicon chips, it is reckoned.

Existing transistors are based on junctions formed by adjacent layers of semiconductor material with different dopant-atom-induced polarities. Since controlling the junction allows current in the device to be turned on and off, it is the precise fabrication of this junction that determines the characteristics and quality of the transistor and is a major factor in production costs. However, as the distance between junctions drops below 10nm, extraordinarily high doping concentration gradients become necessary. Because of the laws of diffusion and the statistical nature of the distribution of the doping atoms, such junctions require increasingly complex and costly fabrication processes.

Tyndall’s new transistor consists of a silicon nanowire (about 30nm across just 10nm thick), and it has no junctions and no doping concentration gradients, since current flow is controlled by a ‘wedding ring’ gate structure around the wire. “These structures are easy to fabricate even on a miniature scale, which leads to the major breakthrough in potential cost reduction,” claims Colinge.

Another key challenge for the semiconductor industry is reducing the power consumption of complex transistors, with minimizing current leakage one of the main challenges. The new transistors — which can be made to have full CMOS functionality — have near-ideal subthreshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors, Tyndall claims. “They have the potential of operating faster and using less energy than the conventional transistors used in today’s microprocessors,” says Colinge.

The junctionless transistor resembles the first ideal transistor structure, proposed in 1925, but to-date no-one had been able to fabricate it, continues Colinge. He attributes Tyndall’s junctionless transistor to the ability to fabricate a silicon nanowire with a diameter of just a few dozen atoms using electron-beam writing techniques and commercial silicon-on-insulator (SOI) wafers.

“We are beginning to talk about these results with some of the world’s leading semiconductor companies, and are receiving a lot of interest in further development and possible licensing of the technology,” says Tyndall’s CEO, professor Roger Whatmore.

The work was funded by Science Foundation Ireland, and is also underpinned by substantial investments in Tyndall by the Department of Enterprise Trade and Employment and the Higher Education Authority, comments Whatmore.

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Source: Semiconductor today - http://www.semiconductor-today.com/news_items/2010/MARCH/TYNDALL_010310.htm

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Visit: www.tyndall.ie/control

(NanoRealm) - Graphene, a one-atom-thick layer of a carbon lattice with a honeycomb structure, has great potential for use in radios, computers, phones and other electronic devices. But applications have been stymied because the semi-metallic graphene, which has a zero band gap, does not function effectively as a semiconductor to amplify or switch electronic signals.
 While cutting graphene sheets into nanoscale ribbons can open up a larger band gap and improve function, 'nanoribbon' devices often have limited driving currents, and practical devices would require the production of dense arrays of ordered nanoribbons — a process that so far has not been achieved or clearly conceptualized.

But Yu Huang, a professor of materials science and engineering at the UCLA Henry Samueli School of Engineering and Applied Science, and her research team, in collaboration with UCLA chemistry professor Xiangfeng Duan, may have found a new solution to the challenges of graphene.

In research to be published in the March issue of Nature Nanotechnology (currently available online), Huang's team reveals the creation of a new graphene nanostructure called graphene nanomesh, or GNM. The new structure is able to open up a band gap in a large sheet of graphene to create a highly uniform, continuous semiconducting thin film that may be processed using standard planar semiconductor processing methods.

"The nanomeshes are prepared by punching a high-density array of nanoscale holes into a single or a few layers of graphene using a self-assembled block copolymer thin film as the mask template," said Huang.

The nanomesh can have variable periodicities, defined as the distance between the centers of two neighboring nanoholes. Neck widths, the shortest distance between the edges of two neighboring holes, can be as low as 5 nanometers.

This ability to control nanomesh periodicity and neck width is very important for controlling electronic properties because charge transport properties are highly dependent on the width and the number of critical current pathways.

Using such nanomesh as the semiconducting channel, Huang and her team have demonstrated room-temperature transistors that can support currents nearly 100 times greater than individual graphene nanoribbon devices, but with a comparable on-off ratio. The on-off ratio is the ratio between the currents when a device is switched on or switched off. This usually reveals how effectively a transistor can be switched off and on.

The researchers have also shown that the on-off ratio can be tuned by varying the neck width.

"GNMs can address many of the critical challenges facing graphene, as well as bypass the most challenging assembly problems," Huang said. "In conjunction with recent advances in the growth of graphene over a large-area substrate, this concept has the potential to enable a uniform, continuous semiconducting nanomesh thin film that can be used to fabricate integrated devices and circuits with desired device size and driving current.

"The concept of the GNM therefore points to a clear pathway towards practical application of graphene as a semiconductor material for future electronics. The unique structural and electronic characteristics of the GNMs may also open up exciting opportunities in highly sensitive biosensors and a new generation of spintronics, from magnetic sensing to storage," she said.

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Source: PhysOrg.com: http://www.physorg.com/news186397884.html
Provided by University of California - Los Angeles: http://www.ucla.edu/
Nature Nanotechnology Paper Abstract: http://www.nature.com/nnano/journal/vaop/ncurrent/full/nnano.2010.8.html

In a just-published paper in the magazine Science, IBM (NYSE: IBM) researchers demonstrated a radio-frequency graphene transistor with the highest cut-off frequency achieved so far for any graphene device - 100 billion cycles/second (100 GigaHertz).


This accomplishment is a key milestone for the Carbon Electronics for RF Applications (CERA) program funded by DARPA, in an effort to develop next-generation communication devices.
The high frequency record was achieved using wafer-scale, epitaxially grown graphene using processing technology compatible to that used in advanced silicon device fabrication.

"A key advantage of graphene lies in the very high speeds in which electrons propagate, which is essential for achieving high-speed, high-performance next generation transistors," said Dr. T.C. Chen, vice president, Science and Technology, IBM Research. "The breakthrough we are announcing demonstrates clearly that graphene can be utilized to produce high performance devices and integrated circuits."

Graphene is a single atom-thick layer of carbon atoms bonded in a hexagonal honeycomb-like arrangement. This two-dimensional form of carbon has unique electrical, optical, mechanical and thermal properties and its technological applications are being explored intensely.
Uniform and high-quality graphene wafers were synthesized by thermal decomposition of a silicon carbide (SiC) substrate. The graphene transistor itself utilized a metal top-gate architecture and a novel gate insulator stack involving a polymer and a high dielectric constant oxide. The gate length was modest, 240 nanometers, leaving plenty of space for further optimization of its performance by scaling down the gate length.
It is noteworthy that the frequency performance of the graphene device already exceeds the cut-off frequency of state-of-the-art silicon transistors of the same gate length (~ 40 GigaHertz). Similar performance was obtained from devices based on graphene obtained from natural graphite, proving that high performance can be obtained from graphene of different origins. Previously, the team had demonstrated graphene transistors with a cut-off frequency of 26 GigaHertz using graphene flakes extracted from natural graphite.

Source: IBM (home;news)